In recent years, increased requirements for faster transmission, increasing miniaturization and increasing weight reduction of electronic equipments promote increasing high-density integration of printed boards. Therefore, build-up processes for stacking interconnects while mutually coupling only inter-layer sections of the printed board via inner via holes are frequently adopted. Among these, processes employing resin sheets with copper foils (Patent Documents 1 and 2) and build-up processes according to semi-additive processes (Patent Documents 3, 4 and 5) are adopted.    [Patent Document 1] Japanese Patent Laid-Open No. H 7-224,252 (1995)    [Patent Document 2] Japanese Patent Laid-Open No. 2002-299,834    [Patent Document 3] Japanese Patent Laid-Open No. 2001-181,375    [Patent Document 4] Japanese Patent Laid-Open No. 2002-241,590    [Patent Document 5] Japanese Patent Laid-Open No. 2005-285,540